1. Field of the Invention
The present invention relates to an electrostatic discharge device which protects a semiconductor device (hereinafter, referred to as an LSI) from an electrostatic discharge (ESD), and particularly to an electrostatic discharge device which protects a device of which breakdown resistance is low such as a micro-transistor for use in operating the LSI at high speed.
2. Description of the Related Art
In recent years, as acceleration and integration of an LSI has been progressed significantly, miniaturization of a device, and particularly, thinning of a gate insulating film of a field-effect transistor (hereinafter, referred to as a MOSTr) has proceeded rapidly. Accordingly, it is necessary that an ESD protection circuit operate at a voltage lower than a voltage at which the gate insulating film of the MOSTr as a device to be protected is broken. In addition, in this case, in order to restrict an influence on high-speed operation performance of the LSI, it is necessary to restrict stray capacitance to be added by the ESD protection circuit to the device to be protected. In order to restrict the stray capacitance to be added, it is necessary to reduce a size of a protection device configuring the ESD protection circuit. However, when the size of the protection device is reduced, there is a problem that the protection device itself is prone to be damaged by ESD stress.
As a conventional example of an ESD protection circuit which can prevent a breakdown of the device to be protected and can also avoid the damage on the protection device itself, for example, there is a protection circuit disclosed in Japanese Patent Laid-Open Publication No. S63-81845 (published in 1988) (hereinafter, referred to as Patent Document 1). FIG. 1 depicts a diagram of the protection circuit disclosed in Patent Document 1.
Referring to FIG. 1, a protection circuit 600 disclosed in Patent Document 1 includes a first diode 604 and a first diode group 608 between an input terminal VIN 601 and a high potential side power supply terminal VDD 602, which are connected to a gate 606 of a field-effect transistor 607. The first diode 604 has an anode and cathode, which are connected to the input terminal VIN 601 and the power supply terminal VDD 602, respectively. The first diode group 608 includes a plurality of diodes connected in series so as to be directed to a forward direction from the power supply terminal VDD 602 side to the input terminal VIN 601 side.
Furthermore, the protection circuit 600 is configured by including a second diode 605 and a second diode group 609 between the input terminal VIN 601 and a low potential side power supply terminal VSS 603. The second diode 605 has an anode and cathode, which are connected to the power supply terminal VSS 603 and the input terminal VIN 601, respectively. The second diode group 609 has a plurality of diodes connected in series so as to be directed to a forward direction from the input terminal VIN 601 side to the power supply terminal VSS 603 side.
Moreover, as the conventional ESD protection circuit operating at the lower voltage for protecting the device of which ESD breakdown resistance is low, for example, there is an input protection circuit disclosed in Japanese Patent Laid-Open Publication No. 2001-148460 (Patent Document 2), or an ESD protection device disclosed in Japanese Patent Laid-Open Publication No. 2002-43533 (Patent Document 3).
FIG. 2A is a circuit diagram of the input protection circuit disclosed in Patent Document 2. FIG. 2B is a cross-sectional view schematically depicting a cross-sectional structure of the circuit in FIG. 2A. Referring to FIG. 2A, in an input protection circuit 700 disclosed in Patent Document 2, a drain (D) of an n-channel MOSTr (hereinafter, referred to as an NMOS)711 is connected to an input terminal VIN, and a source (S) and gate (G) thereof are connected to each other, and these source (S) and gate (G) are connected to a ground (GND).
Meanwhile, a drain (D) of a p-channel MOSTr (hereinafter, referred to as a PMOS) 712 is connected to the input terminal VIN, and a source (S) and gate (G) thereof are connected to a power supply VDD in a state of being connected to each other. Between the power supply VDD and the input terminal VIN, (n3+n4) pieces of diodes 781 connected in series are inserted in a forward direction, and a connection point which divides these diodes 781 into the n3 pieces and the n4 pieces is connected to a substrate (SB) of the PMOS 712.
Furthermore, between the input terminal VIN and the GND, (n1+n2) pieces of diodes 781 connected in series are inserted in a forward direction, and a connection point which divides these diodes 781 into the n1 pieces and the n2 pieces is connected to a substrate (SB) of the NMOS 711.
Note that the number of diodes is determined in the following manner, for example, when the n1 and n2 pieces of diodes 781 are used. Specifically, when a power supply voltage is Vdd and an input voltage Vin to be applied to the input terminal VIN is 0≦Vin≦Vdd, if Vf is a forward voltage of one diode, the number of diodes is set to satisfy the following expression (1):Vdd/(n1+n2)<Vf  (1)
This setting is applied similarly to the n3 and n4 pieces of diodes 781. The expression (1) is a condition for restricting a leak current flowing through the diodes during a normal operation. During the normal operation, the voltage Vdd is applied to both ends of the (n1+n2) pieces of diodes 781 at the maximum, and accordingly, if the voltage Vdd/(n1+n2) distributed to the respective diodes is smaller as compared with the forward voltage Vf, then the leak will be restricted. For example, when the power supply voltage is 3.3V, if the forward voltage Vf is set at 0.33V, a relation: n1+n2>10 (=3.3/0.33) is established because Vdd/Vf<n1+n2 is derived from the expression (1).
Hence, n1 is set at 10, and n2 is set at 1. In this case, the input voltage Vin during the normal operation is present between 0V and 3.3V, a potential on the connection point of the n1 piece of diodes 781 and the n2 piece of diode 781, that is, a substrate potential (SB potential) of the NMOS 711 is changed between 0V and 0.3V which are distributed among the n1+n2 pieces of diodes 781.
With such a configuration, the substrate (SB) of the PMOS 712 or NMOS 711 is biased in response to the input voltage Vin applied to the input terminal VIN. Hence, a snapback trigger voltage Vt1 of the MOSTr on the substrate (SB) which is biased in the forward direction can be lowered, thus making it possible to prevent a gate oxide film of an internal device from being broken by an overvoltage input.
Note that FIG. 2B depicts a cross-sectional structure of the input protection circuit depicted in FIG. 2A. Here, between a circuit portion composed of the NMOS 711 and the n1 and n2 pieces of diodes 781 and a circuit portion composed of the PMOS 712 and the n3 and n4 pieces of diodes 781, only different are conduction types of impurities of the MOSTr portions and the biases therefor. Structures and operations other than the above are in a symmetrical relation and basically the same. Therefore, FIG. 2B only depicts the NMOS 711 and a circuit relating thereto.
FIGS. 3A and 3B are constitutional diagrams of an ESD protection device by the inventor of the present invention. Specifically, FIG. 3A is a circuit diagram of an ESD protection device disclosed in Japanese Patent Laid-Open Publication No. 2002-43533 (Patent Document 3). FIG. 3B is a cross-sectional view schematically depicting a cross-sectional structure of the circuit in FIG. 3A. This ESD protection device 800 operates as an input buffer protection circuit.
Referring to FIG. 3A, this ESD protection device 800 is provided between an input terminal (input pad) 806 of a semiconductor integrated circuit chip and, for example, a CMOS (Complementary Metal Oxide Semiconductor) transistor 880. Furthermore, the ESD protection device 800 includes: a trigger device 850 having diode groups 851 and 852 which conduct by an overvoltage applied to the input terminal 806; and an ESD protection device 820 having vertical bipolar transistors 821 and 822 which conduct by the conduction of the diode groups 851 and 852 and discharge electric charges accumulated in the input terminal 806.
Then, each of the diode groups 851 and 852 has a plurality of diodes connected in series. The overvoltage is a forward voltage for the diode groups 851 and 852.
Note that, with regard to each of the diode groups 851 and 852, FIG. 3A depicts four diodes connected in series. FIG. 3B depicts two diodes connected in series in a simplifying manner for the sake of convenience.
In the diode group 851, a cathode of a first diode is connected to a base of the vertical bipolar transistor 821, and an anode of a last diode is connected to the input terminal 806. In the diode group 852, a cathode of a last diode is connected to a base of the vertical bipolar transistor 822, and an anode of a first diode is connected to a power supply terminal 807. A resistor 833 is connected between the cathode of the first diode of the diode group 851 and a ground terminal 808. A resistor 834 is connected between the cathode of the last diode of the diode group 852 and the input terminal 806.
Both of the vertical bipolar transistors 821 and 822 are of an NPN type. In the vertical bipolar transistor 821, a collector is connected to the input terminal 806, and an emitter is connected to the ground terminal 808. In the vertical bipolar transistor 822, a collector is connected to the power supply terminal 807, and an emitter is connected to the input terminal 806. The resistors 833 and 834 are made of single crystal silicon, polycrystalline silicon, metal or the like, which is formed in the same semiconductor integrated circuit chip. Each of the diode groups 851 and 852 is formed of an N+ diffusion layer 801, a P+ diffusion layer 802, an N-well 805 and the like, which are formed during a normal CMOS process.
This ESD protection device raises base potentials of the vertical bipolar transistors 821 and 822 by a voltage drop when a trigger current caused by the conduction of the diode groups 851 and 852 flows through the resistors 833 and 834, thus turning on the vertical bipolar transistors 821 and 822. In such a way, a large amount of electric charges accumulated electrostatically in the input terminal 806 is discharged in a vertical direction of a silicon substrate, and a large ESD resistance is obtained.
The protection circuit disclosed in Patent Document 1 uses the diode groups in which a plurality of diodes is connected in series. Then, the ESD stress applied to a terminal to be protected is discharged to a discharge terminal of a high potential side power supply terminal, a low potential side power supply terminal or the like by the forward current of the diodes. Therefore, the damage to the protection device can be prevented.
Consequently, an ON resistance in the forward direction when the plurality of diodes are connected in series is increased fairly much, and accompanied with an increase of the discharge current, a potential difference between the terminal to be protected and the discharge terminal is increased radically. Therefore, it is problematic that the protection circuit is applied to the protection of the recent device in which the ESD resistance is low.
As one of means for solving this problem, it is conceived that an electrostatic discharge device is configured such that another current path is formed parallel to the diode groups.
As an example of the above, FIGS. 4A and 4B are views depicting an example where the diodes configuring the diode groups are arranged to be proximate to one another and a parasitic effect when the forward current is flown through the diode groups is used.
FIG. 4A is a schematic plan view. FIG. 4B is a schematic cross-sectional view depicting a cross section on arrow along a line R–R′ of FIG. 4A.
Referring to FIG. 4A, an electrostatic discharge device 900 includes: n-well regions 910, 920 and 930, all of which are formed on a main surface of a p-type silicon substrate 903; and a p-well region 940 surrounding the whole of these. Furthermore, in an inside of the n-well region 910, an n-type diffusion region 911 and a p-type diffusion region 915 are formed. In an inside of the n-well region 920, an n-type diffusion region 921 and a p-type diffusion region 925 are formed. In an inside of the n-well region 930, an n-type diffusion region 931 and a p-type diffusion region 935 are formed. In an inside of the p-well region 940, a p-type diffusion region 945 is formed.
Then, what are connected to each other are: the p-type diffusion region 915 and a first terminal 901; the n-type diffusion region 911 and the p-type diffusion region 925; the n-type diffusion region 921 and the p-type diffusion region 935; and the n-type diffusion region 931 and a second terminal 902. Hence, this electrostatic discharge device 900 has a configuration in which a first diode D1 formed of the n-well region 910 and the p-type diffusion region 915, a second diode D2 formed of then-well region 920 and the p-type diffusion region 925, and a third diode D3 formed of the n-well region 930 and the p-type diffusion region 935 are connected in series in the forward direction between the first terminal 901 and the second terminal 902. Note that the p-type diffusion region 945 is usually connected to a lowest potential power supply of an LSI on which this electrostatic discharge device 900 is mounted.
The inventor of the present invention has recognized that, as in the input protection circuit of Patent Document 2 and the ESD protection device of Patent Document 3, there is a method for using the diode groups as trigger devices, in which the diode groups are provided parallel to the ESD protection device. Specifically, in each of the input protection circuit of Patent Document 2 and the ESD protection device of Patent Document 3, the diode groups formed by interconnecting the forward diodes on multiple stages are inserted between the terminal to be protected and the discharge terminal, parallel to the ESD protection device, so as to obtain the power supply voltage or more. Then, each of the input protection circuit and the ESD protection device uses the diode groups as the trigger devices of the ESD protection device to allow the diode groups to perform a protection operation at a low voltage, thus avoiding the problem of the forward ON resistance of the diodes (discharge capability).
However, in such a configuration, there is a problem that the ESD protection device is required besides the diode groups to cause an increase of an area required for the ESD protection circuit. Moreover, as depicted in FIGS. 2B and 3B, these diode groups are arranged without undergoing such treatments as changing concentrations of p-type impurities among the N-wells 791 (FIG. 2B) in the diodes proximate and adjacent to one another on the p-type substrate and changing concentrations of p-type impurities between the N-wells 805 in FIG. 3B.
Hence, it is an object of the present invention to provide an electrostatic discharge device capable of performing, at a low voltage, a protection operation for a device to be protected, thereby being capable of protecting the device to be protected, of which ESD resistance is small, from ESD as well as controlling stray capacitance to be added to the device.